While trying to determine BSMD relative gains I ran across a problem in the eta plane of module 116 for fill 10471: saturation appears be occuring at a point well below where we would expect it.  This issue persists across the entire fill.  Here is the zero-suppressed and pedestal-subtracted ADC vs. softId plot for eta strips for this module from the first run in the fill, from VPDMB triggered events:

Figure 1: Run 10091089

And for the last run in the fill:

Figure 2: Run 10092049

Attached is a pdf (10471_runs_Adc.pdf) with these two plots and one more for an intermediate run which has the same features, and a pdf (10471_runs_strips.pdf) with a number of ADC distributions for individual eta strips from all three runs I looked at for this fill.

This problem is not one that I could catch when determining BSMD status fill-by-fill as I lacked the statistics, so it's hard to tell if this fill is an abberation or if this is an ongoing problem.