FGT . . . . . . . . . . DAQ

 DAQ related information for FGT

 

APV Readout System Long Cable Test Setup

The APV front-end ASIC which forms the core of the Forward GEM Tracker readout system combines a sensitive preamplifier, switched-capacitor analog memory array, and low-voltage differential analog output buffer.

Operating such an ASIC directly over a long cable, with the analog output digitized at the far end of the cable, potentially presents some challenges. Of course, there are are also opportunities, to minimize the power dissipation inside the inner field cage region, minimize dead materials, and to maximize reliability by placing most of the electronics in an easily serviceable location on the STAR electronics platform.

At IUCF we are constructing a pair of test boards, one which models the APV readout module "ARM", the other which models the APV cable connector board.

Besides testing the performance of the MIT APV motherboards with a long cable interface, this set of test boards is important to:

  • Develop the interface definitions between the IUCF "ARM" and the MIT "APV Motherboard"
  • Demonstrate a low-dropout low-voltage regulator for the APV power, and characterize its performance
  • Demonstrate the control of APV chips and an I2C temperature sensor via the UART - I2C bridge chip
  • Evaluate the effects of various thermal and grounding options for the FGT
  • Run the APV's for detector testing (either with an external ADC and clock source, or with the connector board here and the full ARM to be developed

Here are the design files:

The connector board should be compatible with a pair of FGT APV Motherboards, a total of 10 APV chips. The mock readout board provides only two channels of analog line receiver, testing two different concepts for this. One is a DC coupled line receiver using Analog Devices # AD8129, the other is a transformer-coupled line receiver using a TI # OPA684 opamp. The transformer solution should have superior noise and common-mode rejection and lower power, but it is of course not DC coupled as we would wish. It could be used if DC restoration is applied digitally in the FPGA (on the real ARM).

First results:

Here is the APV readout sequence, looking good:

 

The "noise" which is apparent here is merely crosstalk from the clock signal, and as such will be easily removed by the filter in front of the ADC. Neither that filter nor the cable frequency equalization filter is in place for the measurement above.

Clock frequency was 40 MHz; APV was triggered at 1 kHz from a pulse generator. No inputs connected, no shield box. Cable is Belden 1424A, 110 feet, coiled up on workbench.

ARM - FEE Final Interface Prototype

Details of final prototype of FEE interface circuitry for FGT APV Readout Module "ARM". This includes the isolated remote-regulated power supplies, the isolated I2C line interface, the isolated LVDS clock & trigger line drivers, and the differential analog receiver. Cable connectors and pinouts here are proposed for final application. (In actual ARM, cables interface through a rear transition board in the crate through the 96-pin DIN connector to ARM module. This is not implemented here - cables connect directly using same connector type and pinouts on the cables.)

 

Here are the details:

Brief overview of FGT FEE/Readout electronics chain

This is a short overview of the front end and readout electronics of the FGT. The emphasis is on providing some documentation on all the components. At present most of the items exist only as prototypes, I will try to keep this page current as things get finalized.

First, the front end board, which has 5 APV chips. Two front end boards are used per FGT quadrant (24 quadrants total). One sits at each end of the quadrant. As four quadrants fit together to form an FGT disk, the pairs of front end boards from adjacent quadrants physically sit close to each other. They are serviced by a common cable, interconnect board, and terminator board (to be described shortly).

Below is a picture of the first FGT quadrant (actually just a mechanical test assembly, the pad plane is an old design and is defective). Apologies this is a shiny object photographed on a shiny table in the Bates cleanroom. What you see here is mainly the aluminized mylar gas window which is also the ground plane, sits a couple of mm above the pad plane. On each end of the quadrant is a row of five Samtec MEC6 card-edge connectors (0.635 mm contact pitch): four 140 pin connectors and one 80 pin in the center of the other four. This connects the 640 = 5 APV * (128 ch/APV) signals from the pad plane to the FEE board. The ground is carried separately (see description below). The constraints on FGT inner and outer radius do not permit assigning any of these connector contacts to grounds.

 

Below is a picture of a front end board installed on an FGT quadrant. This is a view from "outside" i.e. this is the side of the front end board that does not have the APV chips. Actually in this picture is a mechanical mockup board, but is mechanically identical to the final design. The white RTV which can be seen in this picture is covering the edge of this quadrant assembly.

 

And here is the actual front end board. In this and the picture above you can see the two ground contact points which will be fastened with screws and washers to wide contact strips extending from the ground foil. This provides the connection of APV signal ground. The ground foil is also similarly connected to the bypass capacitor feeding bias voltage to the bottom of the last GEM foil (connections not detailed here).

Note that it is the back side of this board that would be seen in the quadrant picture above. The two front end boards serviced as a pair have the APV chips mounted on the outward facing sides. Similarly the ground foil connections are made on this outward facing side. From the quadrant's perspective, the chip side of the APV board faces in toward the center of the quadrant.

The front-end board is serviced by the "interconnect board" on one end and a "terminator board" on the other. All interface lines run through from end to end so that the design is symmetrical. Half of the frontend boards have the terminator on the right in this picture, half have the interconnect board on the right. There is only a single flavor of front end board.

The schematic of the front end board is (here). It consist only of five APV chips and a minimal set of support components.

The APV chip is a 128-channel preamp / shaper / SCA / readout mux chip developed for CMS tracker silicon, and also subsequently deployed for GEM readout in COMPASS. Most of the operational details are described in the user guide and in presentations available on the CMS tracker web pages. The APV chip incorporates an analog FIR filter (what the user guide refers to as deconvolution mode) for tail cancellation / pileup reduction at the expense of higher noise. We don't intend to make use of it. It should be noted that the appropriateness of the (fixed) filter coefficients is of course dependent on the sample clock rate. Which is another reason we don't intend to use it.

The APV chip sample clock can be run at least as fast as 40 MHz (as in CMS). For RHIC, we prefer to lock to a multiple of our collision frequency so that the signals can be synchronously sampled avoiding any additional complications or errors from asynchronous sampling. We will use 4x RHIC strobe, 37.532 MHz, a reasonable match to the capability of the APV chip.

The APV chip readout clock can be the sample clock or 1/2 the sample clock rate. With 1/2 the sample clock a single-point readout requires 280/37.532 MHz = 7.46 us. This is amply fast in comparison with other STAR detectors even if multi-point readout is employed. So we will use only the 1/2 rate readout because it significantly eases the signal transport problem.

[Insert here description of the interconnect board / terminator board. (voltage reg, clk/trig receiver, temp sensors, POR circuit, terminations)]

The above comprises the front end electronics subsystem. The interfaces from the front end electronics to the readout electronics are, in total:

  1. Power supplied at +/-1.8 V with remote sense of +1.8, ground, and -1.8 at the terminals of the front end electronics (interconnect board). The power supply is in the readout electronics, and is isolated from ground.
  2. SCL/VSS pair and SDA/VSS pair that connect to the APV chips and other devices, e.g. temperature sensors, on the front end electronics. This I2C interface runs with 2.5 V logic and complies with the I2C standard except in regard to line capacitance limitations where special considerations are taken. The pull-up current source is in the readout electronics. The I2C master in the readout electronics is isolated from ground.
  3. CLK+/- low voltage differential logic signal (continuously running). Source is isolated from ground (transformer coupled) in the readout electronics. The line is terminated at the front end electronics and at the readout board (double-termination).
  4. TRIG+/- low voltage differential logic signal. Source is isolated from ground (transformer coupled) in the readout electronics. The line is double terminated.
  5. 10x (in case of FGT) or up to 12x (in case of IST) analog signal output lines each from one APV chip. All are double terminated and are received at the readout board with a high common-mode impedance line receiver.

(more description/documentation of the readout system to come...)

Event size estimation

 Estimation of FGT event size for pp events @ 500 GeV is 20KB/eve after ZS, physics event will use 80% of this volume.

  1. empty event: 3.7KB Concluding: for 3-sample empty events we need 3.7 KB   300*(2+2+2+2)+30000*(2+2+2+2)/200+100=3700 bytes.
    • total # of channels: 128 ch X 10 APV x4 quad x 6 disks = 30K channels.
    • zero suppression (ZS) is  aiming to keep 1/100 of ADC channels, set to about 3 sigma above ped. Needs testing with data & real electronics, time stability, beam halo, AC-noise . Perhaps we can ZS more.
    • with ZS we need 4 bytes per hit:
      • we need 2 bytes (log2(30k)=14.9) for channel ID
      • ADC value needs up to 12 bits, assume we write it as 16 with 4 bits unused, as with ESMD
    • we may want to keep ADC for 3 time slots per event (using 25 ns integration window) increasing hit size to 8=4+2+2 bytes.
    • it is enough to keep 1/1000 events w/o ZS for monitoring of pedestals
    • event header needs 100 bytes

    2.  

  2. pp data taking
    • assume every track fires 5 strips (will be more at Rin and less at Rout due to varied width of phi strips)
    • trigger event is always embedded in 6 minBias pileup events 
      • at top RHIC luminosity we have 1.5 minB interactions per bXing
      • 300 nsec of analog pulse --> need to account for 4 pre-trigger bXings --> 4x1.5=6 minB eve/trig eve 
      • based on OLD Pythia simulations (obsolete disk size & location) @ 500 GeV one expects 1 track per quadrant per minB event.
      • conclusion: 1440 ADCs will fire due to underlying pileup event   (4 tracks * 6 disks * 2 planes *6 events *5 strips= 1440 

       

    • W-trigger will fire mostly on jets, ASSUME HT consumes lot of jet energy and there is 10 charged (low pT) tracks in such jet. 10 tracks * 6 disks * 2 planes * 5 strips= 600 ADCs. 
      • total physics event content will be 2000 ADC channels. This requires 16KB (2000 *8 bytes)

    3.  

  3.  Heavy Ion even - no study was performed so far.

 

FGT DAQ drawings and hardware documentation

These are the official drawings and documentation used for fabrication of the FGT "DAQ" hardware. We will try to maintain this page up-to-date with any revisions.

APV Readout Controller (ARC)

  • Pictures
  • Schematic (pdf)
  • Schematic (format=?)
  • BOM
  • Layout (format=?)
  • Board fabrication data
  • Assembly data

APV Readout Module (ARM)

ARM Back-of-Crate Board (ABC)

  • Pictures
  • Schematic (pdf)
  • Schematic (Altium)
  • BOM
  • Layout (Altium)
  • Fabrication data files

FGT FEE Patch Panel

  • Pictures
  • Schematic (pdf)
  • Schematic (..)
  • BOM
  • Layout (..)
  • Fabrication data files

Other documentation